In the electronics industry, the tendency has been to reduce the size of electronic devices such as camcorders and portable telephones while increasing performance and speed. Integrated circuit packages for complex systems typically are comprised of multiple interconnected integrated circuit chips. The integrated circuit chips usually are made from a semiconductor material such as silicon or gallium arsenide. The integrated circuit chips may be mounted in packages that are then mounted on printed wiring boards.
Typically, the packages on which these integrated semiconductor chips are mounted include a substrate or other chip-mounting device. Substrates are parts that provide the package with mechanical base support and a form of electrical interface that would allow the external world to access the device housed within the package. When multiple chips are mounted within the same semiconductor package, routing problems may arise due to the different routing design of each individual chip. To solve this problem, an interposer is often used. An interposer is an electrical interface routing between one socket or connection to another. It is an intermediate layer often used for interconnection routing or as a ground/power plane. Sometimes the terms ‘substrate’ and ‘interposer’ are used to refer to the same thing.
A 3D integrated circuit (3D IC) is a single integrated circuit built by stacking silicon wafers and/or dies and interconnecting them vertically so that they behave as a single device. A 3D package contains two or more chips (integrated circuits) stacked vertically so that they occupy less space. Each such chip in such a 3D package could be a conventional chip, a flip chip, or other chips. Conventionally, a single logic die is mounted on silicon using a ball grid array (BGA) package. However, if additional functionality is required, such as flash added to the package stack, 3D IC is needed. Sometimes substrate interposer is used to address the routing problems in 3D IC.
A Package-on-Package (PoP) package is a 3D package in which fully tested packages are stacked on top of one another during the board mount process. A PoP package usually consists of a bottom package and a top package. The bottom package is typically an ASIC or baseband device and the top package may be other functional device such as memory. However, in most 3D packages, the stacked chips are connected together along their edges. And it usually requires extra interposer layers. A laminated substrate is often used for this purpose. Typically both the bottom package and the top package have a laminated substrate. The bottom package has land pads placed on the periphery of the laminated substrate to accommodate the solder balls placed on the periphery of the laminated substrate of the top package. This edge connection on laminated substrate, however, increases the length and width of the package and thus decreases the device density of the package. The current laminated substrate has limited pitch capability.
Typically the laminated substrate can only accommodate semiconductor chips that are not designed for 3D interconnections. Increasingly the semiconductor chips are designed for 3D interconnections. In the front-end-of-line (FEOL) process of semiconductor manufacturing, deep tungsten plugs are routinely fabricated and could serve as via metal interconnecting to other dies. Back-end-of-line (BEOL) process may also be designed for 3D interconnections. In these new technology developments, laminated substrate proves to be inadequate for the modern need of semiconductor 3D interconnections.
Thus, a need still remains for accommodating the modern trend of 3D interconnection design in semiconductor packaging, reducing the package footprint, thickness, and increasing the packaging density. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations and the diminishing opportunities for meaningful product differentiation in the marketplace, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures, adds an even greater urgency to the critical necessity for finding answers to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.